The use of FPGAs for carrying out high speed arithmetic computations has gained recognition in recent years. FPGA architectures including logic blocks having a plurality of look-up-table (LUT) function generators, such as the XC4000.TM. family of devices from XILINX, Inc. (the assignee of the present invention), are particularly suited for such computations. However, many of the important digital signal processing (DSP) algorithms are multiply-intensive, and even FPGAs having a large number of logic blocks and LUTs normally cannot embed the multiplier circuits and the attendant control and support circuits in a single chip. It is therefore incumbent upon the designer to choose efficient DSP algorithms and to realize them with efficient circuit designs. The Fast Fourier Transform (FFT) is an outstanding example of an efficient DSP algorithm. Distributed arithmetic (DA) is a well-established design approach for DSP implementation in FPGAS that replaces gate-consuming array multipliers with more efficient shift and add circuits offering comparable performance.
The FFT is a highly efficient procedure for computing the Discrete Fourier Transform (DFT) of a sampled time series. The DFT, taken from a continuous waveform, is derived from and closely related to the Fourier transform and is particularly useful for digital power spectrum analysis and filtering. The FFT takes advantage of the fact that the coefficients of the DFT can be calculated iteratively, which results in a considerable savings of computation time and a substantial performance advantage over the DFT.
Distributed Arithmetic (DA) was developed as an efficient computation scheme for DSP utilizing FFTS. The DA computation algorithm is now being effectively applied to embed DSP functions in FPGAs, particularly those with coarse-grained look-up table architectures, as described in U.S. patent application Ser. No. 08/937,977. DA enables the replacement of the array multiplier, central to many DSP applications, with a gate-efficient serial/parallel multiplier, with little or no reduction in speed.
U.S. patent application Ser. No. 08/937,977 discloses a space-efficient DA implementation of a DSP circuit implemented in an FPGA using FFTs. In the disclosed circuit, time-invariant systems are implemented using a 16-word, SRAM-based DA look-up table (DALUT). The DALUT contains the pre-computed values of all possible sums of coefficients, weighted by binary values of serial input data. Additional RAM resources are required for the large sine/cosine basis function database. These memory requirements are accommodated using a DALUT containing the pre-computed sums of partial products for combinations of input variables X.sub.rm, X.sub.im, X.sub.rn, X.sub.in and .theta..sub.k, as illustrated in FIG. 1.
The highly space-efficient implementation of a RADIX-2 circuit, illustrated in FIG. 1 and described in U.S. patent application Ser. No. 08/937,977, allows for the implementation of complex FFT circuitry in a single programmable logic device. While the implementation disclosed in the parent case provides a number of significant advantages over the prior art, there remains a need to increase the speed of circuits that benefit from the use of a plurality of RADIX-2 implementations.
The need for multiple RADIXes is apparent from a time series containing N=2.sup.s samples or "points"(where s is the number of stages), wherein the corresponding FFT entails 2sN=2Nlog.sub.2 N multiply operations. For a complete N=1024 point FFT operation on 1024 time-points, a total of 5120 =(N/2*log.sub.2 N=512*10) RADIX-2 operation If only one RADIX-2 is used, since two cycles are required for each RADIX-2 operation, the total time required will be 10240 (5120*2) cycles.
To reduce the number of cycles required for FFT calculations, it appears one need only increase the number of RADIX-2 elements in the circuit and use them simultaneously in each stage. However, two cycles (assuming dual-port RAM is used) are also needed to read and write variables to and from memory, and RAM read and write operations are required for every FFT function, even if additional RADIXes are used. Thus, where only a single RAM is available, there is little, if any, gain in implementation speed from the use of more than one RADIX-2 in a stage. A bottleneck in the data-rate from and to the RAM will retard the function of the circuit. Thus, using k RADIXes in a particular stage does not necessarily provide for k-times speedup of FFT calculations over a single-RADIX implementation. There is therefore a need in the art to which the present invention pertains to optimize FFT implementation for simultaneous use of a plurality of RADIXes.